EEE 6470

Nonclassical Silicon-Based Nanoscale CMOS Devices

Instructor: J. G. Fossum

 

Credits: 3

 

Prerequisite: EEL 6390 or EEL 6397

 

Text: None (journal papers, etc., will be handed out)

 

Content: The course will describe nonclassical Si-based CMOS devices that could eventually replace the classical devices (bulk-Si and partially depleted SOI MOSFETs) when the scaling limit (Lgate ~ 50nm) of the latter is reached, and will assess the scalability of the former to <10nm gate lengths. UFDG, a physics/process-based compact model for double-gate (DG) MOSFETs, linked to Spice3, will be used to illustrate device characteristics and will be made accessible for a class project involving DG CMOS devices and/or circuits.

 

I. Introduction

A. CMOS scaling

B. Problems with nanoscale classical MOSFETs

C. Nonclassical MOSFETs

II. Fully Depleted (FD) SOI MOSFETs

A. Device properties (ultra-thin body (UTB), doping, gate material, etc.)

B. Front-gate/back-gate (substrate) charge coupling

C. Short-channel effects

D. Quantization effects

E. UTB carrier mobility (ballistic transport?)

F. Parasitic bipolar transistor (BJT) effects

G. Single-gate FD/SOI device scalability and design criteria

H. Scaled FD/SOI CMOS performance potential

III. Multi-Gate MOSFETs

A. Triple-gate (and more) vs. double-gate devices (corner effects, layout issues)

B. Symmetrical vs. asymmetrical gates

C. Bulk inversion and effective gate width

D. Gate-source/drain underlap and effective channel length

E. Parasitics (gate overlap/underlap capacitance, series resistances, BJT, GIDL)

F. Scaled DG CMOS design and performance potential

G. DG FinFETs (design and modeling issues)

H. Independent-gate FinFETs (properties and applications)