Prerequisite: EEE 5400, or introductory understanding of semiconductor device physics
Textbook: Fundamentals of Modern VLSI Devices by Y. Taur and T. H. Ning (1998)
Content: The course will cover the criteria and tradeoffs involved in the design of high-performance semiconductor devices in scaled, VLSI (and ULSI) Si-based integrated circuit (IC) technologies where lateral device dimensions are approaching the ultimate limit (~10nm) set by basic lithography restrictions, technology limitations, and/or device physics. Connections to the underlying device physics particularly important to small-geometry devices, and to the IC fabrication process regarding manufacturability, will be stressed. CMOS device (MOSFET) design will be emphasized as reflected by the course outline below. Two mid-term and the final exams, all open-book, will define the course grade.
Inversion carrier-energy quantization
Field-effect on carrier mobility
Source-drain resistance and other parasitics
Non-local effects (hot carriers, velocity saturation and overshoot)