Z. Lu, J. G. Fossum, and Z. Zhou, "A Floating-Body/Gate DRAM Cell Upgraded for Long Retention Time," IEEE Electron Device Lett., vol. 32, pp. 731-733, June 2011.

S. Chouksey, J. G. Fossum, and S. Agrawal, "Insights on Design and Scalability of Thin-BOX FD/SOI CMOS," IEEE Trans. Electron Devices, vol. 57, pp. 2073-2079, Sept. 2010.

J. G. Fossum, Z. Zhou, L. Mathew, and B.-Y. Nguyen, "SOI versus Bulk-Silicon Nanoscale FinFETs," Solid-State Electron., vol. 54, pp. 86-89, Feb. 2010.

S. Chouksey, J. G. Fossum, A. Behnam, S. Agrawal, and L. Mathew, "Threshold Voltage Adjustment in Nanoscale DG FinFETs via Limited Source/Drain Dopants in the Channel," IEEE Trans. Electron Devices, vol. 56, pp. 2348-2353, Oct. 2009.

Z. Zhou, J. G. Fossum, and Z. Lu, "Physical Insights on BJT-Based 1T DRAM Cells," IEEE Electron Device Lett., vol. 30, pp. 565-567, May 2009.

Z. Lu, J. G. Fossum, J.-W. Yang, H. R. Harris, V. P. Trivedi, M. Chu, and S. E. Thompson, "A Simplified, Superior Floating-Body/Gate DRAM Cell," IEEE IEEE Electron Device Lett., vol. 30, pp. 282-284, March 2009.

S. Agrawal and J. G. Fossum, "On the Suitability of a High-k Gate Dielectric in Nanoscale FinFET-CMOS Technology," IEEE Trans. Electron Devices, vol. 55, pp.1714-1719, July 2008.

Z. Lu, J. G. Fossum, W. Zhang, V. P. Trivedi, L. Mathew, and M. Sadd, "A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM," IEEE Trans. Electron Devices, vol. 55, pp. 1511-1518, June 2008.

S. Chouksey and J. G. Fossum, "DICE: A Beneficial Short-Channel Effect in Nanoscale Double-Gate MOSFETs," IEEE Trans. Electron Devices, vol. 55, pp. 796-802, March 2008.

S.-H. Kim and J. G. Fossum, "Design Optimization and Performance Projections of Double-Gate FinFETs with Gate-Source/Drain Underlap for SRAM Application," IEEE Trans. Electron Devices, vol. 54, pp. 1934-1942, Aug. 2007.

J. G. Fossum, Z. Lu, and V. P. Trivedi, "New Insights on "Capacitorless" Floating-Body DRAM Cells," IEEE Electron Device Lett., vol. 28, pp. 513-516, June 2007.

M. M. Chowdhury, V. P. Trivedi, J. G. Fossum, and L. Mathew, "Carrier Mobility/Transport in Undoped-UTB DG FinFETs," IEEE Trans. Electron Devices, vol. 54, pp. 1125-1131, May 2007.

J. G. Fossum, "Physical Insights on Nanoscale Multi-Gate CMOS Design," Solid-State Electron., vol. 51, pp. 188-194, Feb. 2007.

V. P. Trivedi, J. G. Fossum, and W. Zhang, "Threshold Voltage and Bulk-Inversion Effects in Nonclassical CMOS Devices with Undoped Ultra-Thin Bodies," Solid-State Electron., vol. 51, pp. 170-178, Jan. 2007.

S.-H. Kim, J. G. Fossum, and J.-W. Yang, "Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices with Gate-Source/Drain Underlap," IEEE Trans. Electron Devices , vol. 53, pp. 2143-2150, Sept. 2006.

M. M. Chowdhury and J. G. Fossum, "Physical Insights on Electron Mobility in Contemporary FinFETs," IEEE Electron Device Lett., vol. 27, pp. 482-485, June 2006.

S.-H. Kim, J. G. Fossum, and V. P. Trivedi, "Bulk Inversion in FinFETs and Implied Insights on Effective Gate Width," IEEE Trans. Electron Devices, vol. 52, pp. 1993-1997, Sept. 2005.

V. P. Trivedi and J. G. Fossum, "Quantum-Mechanical Effects on the Threshold Voltage of Undoped Double-Gate MOSFETs," IEEE Electron Device Lett., vol. 26, pp. 579-582, Aug. 2005.

J.-W. Yang and J. G. Fossum, "On the Feasibility of Nanoscale Triple-Gate CMOS Transistors," IEEE Trans. Electron Devices, vol. 52, pp. 1159-1164, June 2005.

V. Trivedi, J. G. Fossum, and M. M. Chowdhury, "Nanoscale FinFETs with Gate-Source/Drain Underlap," IEEE Trans. Electron Devices, vol. 52, pp. 56-62, Jan. 2005.

J. G. Fossum, L.-Q. Wang, J.-W. Yang, S.-H. Kim, and V. P. Trivedi, "Pragmatic Design of Nanoscale Multi-Gate CMOS," Tech. Digest 2004 Internat. Electron Devices Meeting, pp. 613-616, Dec. 2004.

V. P. Trivedi, J. G. Fossum, and F. Gámiz, "A Compact QM-Based Mobility Model for Nanoscale Ultra-Thin-Body CMOS Devices," Tech. Digest 2004 Internat. Electron Devices Meeting, pp. 763-766, Dec. 2004.

J. G. Fossum, L. Ge, M.-H. Chiang, V. P. Trivedi, M. M. Chowdhury, L. Mathew, G. O. Workman, and B-Y. Nguyen, "A Process/Physics-Based Compact Model for Nonclassical CMOS Device and Circuit Design," Solid-State Electron., vol. 48, pp. 919-926, June 2004.

J. G. Fossum, M. Chowdhury, V. P. Trivedi, T.-J. King, Y.-K. Choi, J. An, and B. Yu, "Physical Insights on Design and Modeling of Nanoscale FinFETs," Tech. Digest 2003 Internat. Electron Devices Meeting, pp. 679-682, Dec. 2003.

J. G. Fossum, J.-W. Yang, and V. P. Trivedi, "Suppression of Corner Effects in Triple-Gate MOSFETs," IEEE Electron Device Lett., vol. 24, pp. 745-747, Dec. 2003.

Z. Zhou, Physical Analysis, Modeling, and Design of Nanoscale FinFET-Based Memory Cells, 2010.

Z. Lu, Physical Analysis and Design of Nanoscale Floating-Body DRAM Cells, 2010.

S. Chouksey, Modeling, Design, and Performance of Nanoscale Double-Gate CMOS, 2009.

S. Agrawal, Modeling and Optimal Design of Nanoscale Double-Gate CMOS Devices and Technology, 2009.

S.-H. Kim, Nonclassical Nanoscale CMOS: Performance Projections, Design Optimization, and Physical Modeling, 2006.

M. M. Chowdhury, Physical Analysis, Modeling, and Design of Nanoscale Double-Gate MOSFETs with Gate-Source/Drain Underlap, 2006.

W. Zhang, Physics-Based Modeling and Analysis of Nonclassical Nanoscale CMOS, with Circuit Applications, 2006.

V. P. Trivedi, Physics and Design of Nonclassical Nanoscale CMOS Devices with Ultra-Thin Bodies, 2005.

J.-W. Yang, Analysis and Modeling of Parasitic Effects in Advanced Silicon-on-Insulator CMOS Technologies, Including Nonclassical Ultra-Thin-Body Transistors, 2004.

L. Ge, Physical Modeling and Analysis of Carrier Confinement and Transport in Silicon-on-Insulator and Double-Gate CMOS Devices and Circuits, 2002.

M.-H. Chiang, Process-Based Compact Modeling and Analysis of Silicon-on-Insulator CMOS Devices and Circuits, Including Double-Gate MOSFETs, 2001.

K. Kim, Design and Analysis of Double-Gate CMOS for Low-Voltage Integrated Circuit Applications, Including Physical Modeling of Silicon-on-Insulator MOSFETs, 2001.